Plasma enhanced physical vapor deposition (PECVD) processes are used to deposit metal films such as copper onto semiconductor wafers to form electrical interconnections. A high level of D.C. power is applied to a copper target overlying the wafer in the presence of a carrier gas, such as argon. Plasma source power may be applied via a coil antenna surrounding the chamber. PECVD processes typically rely upon a very narrow angular distribution of ion velocity to deposit metal onto sidewalls and floors of high aspect ratio openings. One problem is how to deposit sufficient material on the sidewalls relative to the amount deposited on the floors. Another problem is avoiding pinch-off of the opening due to faster deposition near the top edge of the opening. As miniaturization of feature sizes has progressed, the aspect ratio (depth/width) of a typical opening has increased, with microelectronic feature sizes having now been reduced to about 22 nanometers. With greater miniaturization, it has become more difficult to achieve minimum deposition thickness on the sidewall for a given deposition thickness on the floor or bottom of each opening. The increased aspect ratio of the typical opening has been addressed by further narrowing of the ion velocity angular distribution, through ever-increasing wafer-to-sputter target distance and ever lower chamber pressures, e.g., less than 1 mT (to avoid velocity profile widening by collisions). This has given rise to a problem observed in thin film features near the edge of the wafer: At extremely small feature sizes, a portion of each high aspect ratio opening sidewall is shadowed from a major portion of the target because of the greater wafer-to-target gap required to meet the decreasing feature size. This shadowing effect, most pronounced near the wafer edge, makes it difficult if not impossible to reach a minimum deposition thickness on the shadowed portion of the side wall. With further miniaturization, it has seemed a further decrease and chamber pressure (e.g., below 1 mT) and a further increase in wafer-sputter target gap would be required, which would exacerbate the foregoing problems.
One technique employed to supplement the side wall deposition thickness is to deposit an excess amount of the metal (e.g., Cu) on the floor of each opening and then re-sputter a portion of this excess on the opening side wall. This technique has not completely solved the shadowing problem and moreover represents an extra step in the process and a limitation on productivity.
A related problem is that the sputter target (e.g., copper) must be driven at a high level of D.C. power (e.g., in the range of kW) to ensure an adequate flow of ions to the wafer. Such a high level of D.C. power rapidly consumes the target (driving up costs) and produces an extremely high deposition rate so that the entire process is completed in less than five seconds. This time is about 40% of the time required for the RF source power impedance match to equilibrate following plasma ignition, so that about 40% of the process is performed prior to stabilization of the impedance match and delivered power.